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Several often overlooked details about PCB vias
Especially when the density of vias is high, it may cause the slot to break, isolating the circuit on the copper layer. To solve this problem, in addition to moving the position of the vias, we can also consider reducing the pad size of the PCB vias on the copper layer.
Vias are one of the key components of multilayer PCBs, used to achieve electrical connections between different layers of the PCB. This article introduces some points to note when designing PCB vias.
PCB vias can be divided into two categories according to their function: one is used as an electrical connection between layers, and the other is used for fixing or positioning devices.
From a process point of view, PCB vias are generally divided into three categories: blind vias, buried vias, and through vias.
1. Blind vias
The holes are located on the top and bottom surfaces of the PCB, used to connect the surface circuit to the inner layer circuit. In addition, the depth of the hole usually does not exceed a certain proportion (hole diameter).
2. Buried Vias
These are connecting holes located in the inner layers of the PCB that do not extend to the surface of the circuit board.
Both of the above types of holes are located in the inner layers of the circuit board. They are completed using a through-hole forming process before lamination, and multiple inner layers may overlap during the through-hole processing.
3. Through Vias
This type of PCB via penetrates the entire circuit board and can be used for internal interconnection or as a mounting location for components. Because through vias are easier to manufacture and less expensive, most PCB manufacturers often use them to replace the other two types of PCB vias.
PCB Via Dimensions
From a design perspective, PCB vias are mainly composed of two parts: the central drilled hole and the pad area around the drilled hole. The sizes of these two parts determine the size of the PCB via.
Obviously, in high-speed, high-density PCB design, designers always believe that PCB vias should be as small as possible, so that more routing space can be left on the board. Smaller vias also have smaller parasitic capacitance, making them more suitable for high-speed circuits.
However, reducing the via size also increases the cost. Via size cannot be reduced without limit. Affected by drilling and plating processes, smaller PCB vias take longer to drill and are more likely to deviate from the center. When the via depth exceeds 6 times the drilling diameter, it is difficult to ensure uniform copper plating on the via walls.
For example, for a typical 6-layer PCB with a thickness (through-hole depth) of 50 mils, the drilling diameter provided by the PCB manufacturer is generally only 8 mils.
With the development of laser drilling technology, the size of the drilled holes can also become smaller. PCB vias with a diameter less than or equal to 6 mils are generally called micro vias and are often used in HDI (high-density interconnect) designs. This technology allows PCB vias to be placed directly on the pads (Via-in-pad), greatly improving circuit performance and saving routing space.
Vias are discontinuous impedance points on transmission lines and can cause signal reflections. Generally, the equivalent impedance of a PCB via is about 12% lower than the equivalent impedance of the transmission line. For example, a 50-ohm transmission line will generally have its impedance reduced by 6 ohms after passing through a PCB via.
Parasitic Inductance of Vias
Similarly, PCB vias have both parasitic inductance and parasitic capacitance. In high-speed digital circuit design, the harm caused by via parasitic inductance is often greater than the impact of parasitic capacitance. The parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power supply system.
We can use the following formula to simply calculate the approximate parasitic inductance of a via:
L=5.08h[ln(4h/d)+1]
Via Design in High-Speed PCBs
Through the above analysis of the parasitic characteristics of vias, it is clear that even simple vias can often have a significant negative impact on PCB design in high-speed PCB design.
To reduce the adverse effects of PCB via parasitic effects, please note the following points.
1. Choose a reasonable size PCB via considering both cost and signal quality.
For example, in the design of 6-10 layer memory module PCBs, it is best to use 10/20 mil (drill hole/pad) vias. For some high-density, small-size boards, 8/18 mil vias can be tried.
Under current technological conditions, it is difficult to use smaller vias. For power or ground vias, consider using larger sizes to reduce impedance.
2. From the two formulas discussed above, we can conclude that using thinner PCBs helps reduce the two parasitic parameters of PCB vias.
3. Power and ground pins should be drilled nearby.
In addition, the traces between the vias and the pins should be as short as possible to increase inductance. At the same time, the power and ground traces should be as thick as possible to reduce impedance.
4. Try not to change the layer of signal traces on the PCB. In other words, minimize unnecessary vias.
5. Place some ground vias near the vias where the signal changes layers to provide a closed loop for the signal. You can even place a large number of redundant ground vias on the PCB.
The via model discussed above assumes that there are pads on each layer. Sometimes, we can reduce or even remove the PCB pads on certain layers.
Especially in cases with high via density, this may cause breaks and isolate the circuits on the copper layer. To solve this problem, in addition to moving the position of the vias, we can also consider reducing the pad size of the PCB vias on the copper layer.
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