Design professionals often discuss Design for Manufacturing (DFM) guidelines, but what exactly are they? How are they implemented in your PCB design software? In PCB development, the meaning of DFM is quite simple: design choices should only be implemented if you can ensure that they are manufacturable at a reasonable scale. This seemingly simple explanation omits a lot, so it's natural to assume that your manufacturer can produce anything you put into your PCB layout in your design software.

　　In reality, different manufacturers have different capabilities, material selections, and standard contactless service options. There are some very common mistakes or oversights that can render a board unmanufacturable and may require significant redesign. In this article, I will cover some common mistakes that both novice and experienced designers may make. I've made these mistakes myself, but I can tell you that you can always recover from them and ensure your board is manufacturable.

　　 Some basic PCB design manufacturing tips

　　The points I will outline below almost entirely concern two important areas:

　　Material considerations, especially core/laminate materials and copper weight

　　Manufacturing constraints, especially feature sizes and clearances in the PCB layout

　　With that in mind, let's jump right into some basic PCB design manufacturing guidelines needed to ensure a successful design.

　 　Get the layer stackup first

　　You'd be surprised how easy it is to jump right into a new design and start placing components on the board. For simple boards that don't require controlled impedance, specific bus capacitance, or dense digital routing, you can start placing directly on an even-layered board with standard layer thicknesses. Depending on the design, the manufactured PCB may not perform as you expect.

　　For most designs, even microcontroller boards for hobbyist use, you need to at least understand the layer stackup and material properties. Before you start routing digital buses or any controlled impedance traces, email your manufacturer and get their standard layer stackup. If you don't, the manufacturer may produce your board using a layer stackup that doesn't produce the functionality you expect. Another risk is that you create a layer stackup that they can't manufacture, usually because they don't have the materials in stock to meet your stackup specifications.

　 　Match copper weight to current density and laminate

　　Don't be surprised if your manufacturer rejects your copper weight when you select materials or get stackup approval. You need to use the copper weights available on the manufacturer's material set; you can't just specify any copper weight you want. If you take the time to estimate the copper weight and trace width required for a particular current density (e.g., power rails), then you should ensure that you specify the required weight when determining the stackup with the manufacturer.

　 　Reinforce clearances between copper

　　When you start a new PCB layout, your ECAD software will apply a set of default clearance rules that are conservative values suitable for almost all PCBs. These values are often overly conservative, so they are usually ignored without entering the correct clearance values before starting the layout. Worse, you may enter values that are too small, which will allow you to place elements too close together, making the board unmanufacturable.

　　Note the polygon near this trace: The DRC engine has flagged a clearance error along the length of the trace in this window. Trace-to-polygon clearance rules should be set to ensure that these elements are not too close, otherwise unexpected shorts may occur between these elements during manufacturing.

　　Solution: Understand your manufacturer's limitations before you start placing and incorporate these values as design rules into your PCB project. If you want to ensure that common clearance violations are met, pay attention to the following clearances:

　　Trace to trace;

　　Trace/fill to polygon;

　　Trace to pad;

　　Pad to pad;

　　The last two points apply to landing pads for SMD pads and through-hole (via or component lead) pads. Note that these values will be larger for heavier copper due to the need for etch compensation.

　　 Overlapping Drill Holes

　　If you've followed the previous clearance guidelines and set smaller pad-to-pad spacing values, then you may have already addressed this design manufacturing guideline. If the distance between drill points is too close, they may overlap each other due to the offset of the CNC drilling machine. Each drill point will deviate slightly from its ideal drill location, and this needs to be considered when placing vias and through-hole leads.

　　Note that even if you adhere to the pad-to-pad clearance of vias and through-hole leads, it may not guarantee that you meet the drill-hit clearance. Suppose you place a 10mil via with a 12mil pad; if your pad-to-pad clearance limit is only 5mil, but the drill-to-drill clearance is 10mil, then you will violate the drill-hit limit by 3mil if you only adhere to the pad-to-pad limit.

　　Similar problems can occur between drills that pass through planes, such as the heatsink and GND plane clearance shown below. The two green areas show the clearance between the via walls and the plane for these nets; the remaining sliver here is too small to manufacture. The specific example shown below is an example where this type of manufacturing failure will not cause the device to malfunction, but this may not be the case in general. If this defect is located on the surface layer between two vias, there is a risk of bridging during soldering, as the narrow copper feature is likely to be etched away during manufacturing.

　　The spacing between these two vias is so small that only a very small sliver of copper remains on the plane layer, which will be over-etched and will not appear on the finished board.

　　The natural solution here is to use larger pads, which is exactly what is done to meet basic IPC class requirements; use a smaller pad size (drill diameter) + 8mil to ensure that you almost always meet the drill-to-drill clearance limit.

　 　Small Feature Sizes

　　When you start populating components and routing on your board, you may be tempted to make your traces, drill points, and pads too small. Clearance rules have already limited how close you can place everything, but equally important design requirements are minimum feature sizes. Two common issues you need to address are minimum hole size and trace width. This is simple; just look up your manufacturer's feature sizes and incorporate them into your design rules. Typical manufacturing limits that apply to most boards are 4mil trace width and 6mil drill width. For many simpler boards that don't require controlled impedance, use 8-10mil trace width and 10mil drill diameter.

　 　Solder Mask Sliver

　　This is an often overlooked aspect of assembly, aimed at ensuring that solder mask openings reliably prevent molten solder from flowing between two adjacent components. Even with adequate spacing between pads, excessively large solder mask openings on NSMD pads can leave very thin solder mask pathways between pads.

　 　Solder Mask Debris Error

　　The remaining solder mask sliver between Q9 and Q10 is unmanufacturable because it is too thin. However, the pad-to-pad clearance still meets requirements. The solution here is to reduce the solder mask opening on these pads to 0mil. You may also need to increase the spacing between these components by a few mils.

　　A typical minimum solder mask sliver here is 5mil. When the solder mask sliver is below the manufacturer's limit, it may break after curing and form a channel where the two pads can be bridged by solder. The solution here is to apply additional spacing, or reduce the solder mask opening on the affected pads to retain a sufficiently large sliver.

　　Overlapping Silkscreen

　　After layout and routing, the silkscreen should be checked to ensure there are no overlapping reference designators. If there are, you can move them in the PCB layout until everything is clear. While not technically a requirement for successful manufacturing or assembly, diligent manufacturers will still flag this as an issue during design review.